Implementation of an XOR Based 16-bit Carry Select Adder for Area, Delay and Power Minimization

Abstract

In different types of processors and other digital circuits adders are most widely used. Low power and area efficient high-speed circuits are most substantial area in the research of VLSI design. The carry select adder is one of the fast adders which has less area and reduced power consumption. In this paper, a 16-bit carry select adder has been presented using modified XOR based full adder to reduce circuit complexity, area and delay. The modified full adder design requires only two XOR gates and one multiplexer. The modified 16-bit carry select adder gives better result than conventional carry select adder with respect to area, power consumption and delay.