Abstract
A real-time stereo digital audio decoder based on one 16-b digital signal processor (DSP) chip, implementing the decoder portion of an audio compression system, is described. The roundoff-sensitive portions of the decoder include pre multiplier and conventional inverse FFT operations, which have been efficiently coded with mixed-precision 16-b by 32-b multiplies with 32-b accumulations. Compared with a 16-b single-precision implementation, a moderate increase in DSP CPU utilization is incurred. Results indicate that the dynamic range of the 16-b DSP decoder is currently within 1 to 3 dB of the limitations imposed by high-quality 16-b A/D and D/A converters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
