Abstract
In this study, the efficient fabrication of nickel silicide (NiSix) Schottky barrier thin-film transistors (SB-TFTs) via microwave annealing (MWA) technology is proposed, and complementary metal-oxide-semiconductor (CMOS) inverters are implemented in a simplified process using ambipolar transistor properties. To validate the efficacy of the NiSix formation process by MWA, NiSix is also prepared via the conventional rapid thermal annealing (RTA) process. The Rs of the MWA NiSix decreases with increasing microwave power, and becomes saturated at 600 W, thus showing lower resistance than the 500 °C RTA NiSix. Further, SB-diodes formed on n-type and p-type bulk silicon are found to have optimal rectification characteristics at 600 W microwave power, and exhibit superior characteristics to the RTA SB-diodes. Evaluation of the electrical properties of NiSix SB-TFTs on excimer-laser-annealed (ELA) poly-Si substrates indicates that the MWA NiSix junction exhibits better ambipolar operation and transistor performance, along with improved stability. Furthermore, CMOS inverters, constructed using the ambipolar SB-TFTs, exhibit better voltage transfer characteristics, voltage gains, and dynamic inverting behavior by incorporating the MWA NiSix source-and-drain (S/D) junctions. Therefore, MWA is an effective process for silicide formation, and ambipolar SB-TFTs using MWA NiSix junctions provide a promising future for CMOS technology.
Highlights
Metal silicides, i.e., compounds of metal and silicon (Si), have been widely employed as interconnecting and contact materials in complementary metal-oxide-semiconductor (CMOS) technology due to their low specific resistivity, low contact resistivity towards both types of Si, high thermal stability, good processibility, and excellent process compatibility with standard Si technology [1,2,3,4]
Source-and-drain (S/D) junctions have aroused much interest in nanoscale metal-oxidesemiconductor field-effect transistors (MOSFETs) because the resistive–capacitive (RC) time delay must be reduced by minimizing both parasitic resistance and capacitance components, in order to meet the major requirement of speeding up electronic circuits [5,6,7]
These results suggest that the charge trapping process is driven by thermal activation
Summary
I.e., compounds of metal and silicon (Si), have been widely employed as interconnecting and contact materials in complementary metal-oxide-semiconductor (CMOS) technology due to their low specific resistivity, low contact resistivity towards both types of Si, high thermal stability, good processibility, and excellent process compatibility with standard Si technology [1,2,3,4]. In. SB-MOSFETs, the S/D junction consists of silicide in place of conventional impurity-doped silicon, enabling lower parasitic series resistance and ultrashallow abrupt junction formation via a simpler process [7,8,9,10]. In the case of TiSix , the sheet resistance (Rs ) increases as the line width decreases [11,12,13,14], while in the case of CoSix , junction spiking becomes an issue due to excessive Si consumption [12,15,16].
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