Abstract
The commencement of decryption process of Advanced Encryption Standard (AES) algorithm is dependent on availability of the last round key. In this paper, we propose a look-ahead technique for increasing the speed of implementation of AES key schedule using which the last round key can be made available fast. The other round keys can also be computed in a parallel path using the proposed technique. Applications such as key search engines need to be agile to key changes for decrypting given encrypted messages using all the keys in the available key space so that fast decryption is possible. The FPGA implementation results using Xilinx XC5VLX85 are also provided.
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