Implementation of a veto processing hardware

Abstract

This paper describes the implementation of a piece of general purpose events veto processing hardware, in the form of a custom integrated circuit and a minimum of additional components, for use with pixel-type detectors, in particular those requiring the technique of Time-walk correction and multi-trigger association. This work was carried out as a part of the design study for a gamma-ray imager experiment such as the one proposed for the Integral spacecraft mission. The design can handle up to 3072 detector elements, grouped into 24 separate detector modules (consisting of up to 128 detector elements each) in addition to a veto shield detector module. The system will be capable of handling a maximum average detector trigger rate of 10 000 triggers/s and veto shield trigger rate of 70 000 triggers/s without saturating the system. Analysis of an operational model of the gamma-ray imager under study results in 1400 valid events/s where on average there are 1.75 triggers per event. This will result in data reduction factor of 4. The IC can also perform triggers to events associations thus, further reducing the workload on the rest of the experiment's central data processing system. This study shows that a single ASIC solution is viable using for example a XILINX IC, three 8 k × 8 SRAMs and a single 512 k × 1 bit serial ROM.