Implementation of a high speed multiplier for high-performance and low power applications

Abstract

The performance of multiplication in terms of speed and power is crucial for most of the Digital Signal Processing (DSP) applications. Many researchers have come up with various multipliers such as array, Booth, carry save, Wallace tree and modified Booth multipliers. However, for the present day applications Vedic multipliers based on Vedic Mathematics are presently under focus due to their high speed and low power consumption. In this paper, we propose a design of 8 and 16-bit multipliers using fast adders (carry save adder, Brent-Kung adder and carry-select adder) to minimize the power-delay product of multipliers intended for high-performance and low-power applications. Implementation results demonstrate that the proposed Vedic multipliers with fast adders really achieve significant improvement in delay, and power-delay product when compared with the conventional multipliers.