Abstract
SPIDER (SEMATECH Process-Induced Damage Effect Revealer) is a test vehicle containing a variety of test structures for evaluation of electrical damage during integrated circuit manufacturing. Each of its test modules is designed to characterize damage from a specific process or sequential processes, such as implant and etch at different levels. The test modules used in this study consist of MOS transistors with each of their gates connected to a polysilicon rectangular antenna over field oxide. The area ratio of the polysilicon antenna to gate varies from 62,220:1 to 20:1. The test procedure is as follows. First basic parameters of MOS transistor are measured. Subsequently, the gate oxide is stressed by Fowler-Nordheim (F-N) stress at a constant current density of 5 nA/cm2. The same MOS transistor parameters are measured again, then retested; its oxide is stressed by a constant current density of 5 nA/cm2. Then the MOS transistor parameters are measured again. The FN stress reveals eventual latent damage passivated by annealing which always follows the damage causing process. The test devices were manufactured using a standard CMOS process.
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