Impacts of random telegraph noise (RTN) on the Energy-Delay tradeoffs of logic circuits

Abstract

In this paper, the impacts of random telegraph noise (RTN) on delay and energy of digital logic circuits are studied. The conventional method of extracting logic gate delay is found inaccurate due to the bias dependency of RTN amplitude. Thus an appropriate measuring strategy is proposed, based on which the impact of single RTN on circuit delay is investigated, and non-monotonous trend against trap energy level Et is found. Furthermore, the impacts of multi RTN on Energy-Delay(ED) curves are discussed. It is found that RTN is unneglectable when performing an ED optimization. Otherwise, under-design phenomenon would occur considering delay constraint, and over-design would occur considering energy constraint. This result provide helpful guidelines for circuit design.