Impacts of Random Telegraph Noise on FinFET devices, 6T SRAM cell, and logic circuits

Abstract

This paper analyzes the impacts of single trap induced Random Telegraph Noise (RTN) on scaled FinFET devices in tied-gate and independent-gate modes, 6T SRAM cell and logic circuits. The dependence of RTN amplitude on trap location, EOT and temperature is evaluated through 3D atomistic TCAD simulations. It is observed that charged trap located near the bottom of sidewall (gate) interface, in the middle region between the source/drain results in most significant impact. EOT scaling and higher temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependency on the location of the trap and current conduction path are analyzed. We show that planar BULK device, with larger Subthreshold Swing (S.S.) and comparable trap-induced V T shift (ΔV T ), exhibits less nominal RTN degradation than FinFET for trap placed in the worst position. However, the larger variability and surface conduction characteristic of planar BULK device result in broader dispersion and larger worst-case degradation than FinFET with smaller variability and volume conduction inside the silicon fin. For FinFET 6T SRAM cell, the READ Static Noise Margin (RSNM) of 64 possible combinations from trapping/de-trapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V dd ), the relative importance of RTN on the cell stability increases. The leakage/delay of FinFET inverter, 2-Way NAND and 2-To-1 multiplexer are investigated using mixed-mode TCAD simulations. The existence of RTN is found to cause ∼24–27% and 13–15% variation in leakage and delay at V dd =0.4V, respectively, for the logic circuits evaluated.