Impact of virtual substrate growth on high performance strained Si/SiGe double quantum well metal-oxide-semiconductor field-effect transistors

Abstract

Strained Si/SiGe n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated using a dual quantum well structure. The heterostructure is designed for maximum performance from both n- and p-channel devices using a single Si0.85Ge0.15 virtual substrate. An optimized thermal budget has been used for device fabrication, which was possible due to the strain-compensated layer structure providing increased material robustness to strain relaxation. Epitaxial growth has been carried out by low-pressure chemical vapor deposition (LPCVD) at two different temperatures. Strained Si MOSFETs fabricated on virtual substrates grown at high temperature exhibited drain current enhancements three times as large as those demonstrated by strained Si MOSFETs fabricated on material grown at low temperature, compared with control Si devices. Detailed material analysis suggests that the higher degree of surface roughness and higher defect density of the low temperature LPCVD material limits the performance enhancements achievable due to the increased carrier scattering in these devices. Nevertheless, the results demonstrate that by incorporating strain-compensated Si/SiGe layers into conventional Si MOSFETs, even degraded SiGe material can offer performance advantages over bulk Si devices. However, high temperature material growth is required to achieve both maximum performance gains and the same degree of uniformity as that achieved from bulk Si technologies.