Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Abstract

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (Ion), OFF current (Ioff) and Ion/Ioff ratio. The potential benefits of SOI FinFET at drain-to-source voltage, VDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (AV), output conductance (gd), trans-conductance (gm), gate capacitance (Cgg), and cut-off frequency (fT = gm/2πCgg) with spacer region variations.