Impact of carrier quantum confinement on the short channel effects of double-gate silicon-on-insulator FINFETs

Abstract

In this work, we use a center potential based approach to determine the electrostatics viz. threshold voltage (Vth), Sub-Threshold Slope and Drain Induced Barrier Lowering (DIBL) for Fully Depleted (FD) Undoped Symmetric Double-Gate (DG) Silicon-on-Insulator (SOI) FINFETs over a wide range of Channel Lengths (Lg) and drain voltages (Vd). Based on this approach, a comparison of the electrostatics of Undoped Symmetric Double-Gate (DG) Silicon-on-Insulator (SOI) FINFETs is presented between the semi-classical and quantum confinement cases for two different SOI fin thicknesses of Tfin=2nm and Tfin=7nm, respectively. For both cases, it is observed that the threshold voltage roll-off and DIBL is greater in the quantum confinement case than in the semi-classical case. This seemingly counter-intuitive trend also implies that the channel length corresponding to the transition from long channel to short channel behavior (Lmin) is also lower in the semi-classical case compared to the quantum confinement case. This behavior is explained by comparing the Lateral Electric field (along the channel length) with the Electric Field along the thickness of the SOI fin for Tfin=2nm and Tfin=7nm over a wide range of gate and drain voltages. This analysis suggests that quantum confinement adversely affects the short channel effects and leads to an increase in the Lmin compared to the semi-classical case. These results for Lmin clearly illustrate the importance of the need to include the quantum confinement effects while evaluating the electrostatics performance and scalability of symmetric DG SOI FINFETs.