Abstract
It is well-known that continuous operation of semiconductors under electrical and thermal overload conditions leads to degradation and subsequently to device failure. This paper deals with wirebond and metallization degradation of integrated vertical DMOS switches that are stressed with periodic power dissipation pulses under laboratory conditions. The test setup is briefly described as well as the test results. Physical failure analysis proves that migration phenomena in the power metallization, as well as bond wire delamination, play a crucial role in device aging. A model of time to failure is derived from measured data. It implies that thermomechanical as well as electrical mechanisms contribute to final device failure. Several hypotheses are discussed, showing that the wirebond-metallization interface is most probably the weak point of power switch robustness. Further tasks will therefore include evaluating possible improvements on power metallization and bond connection reliability.
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