Abstract
Nanosheet Field Effect Transistor (NSFET) has emerged as a promising candidate to replace FinFET devices at sub-7nm technology nodes and for different SoC applications. In this work, we have investigated the DC properties of 3D vertically-stacked NSFET including the impact of self-heating effect (SHE) and also influence of geometry scaling. The thermal resistance and the maximum lattice temperature have been analyzed according to the device’s channel number. Also, the distribution of lattice temperature has been exposed. During the 3D investigation, it has been observed that SHE degrades the switching performance and subthreshold swing SS ≈ 22%. Furthermore, it is found that the proposed device is showing improved figure of merits as ION (∼2.77 × 10−5A), IOFF (∼10−20A), SS (>60 mV decade−1) and ION/IOFF (∼1015). The DIBL has been reduced by −52% when the NS’s width is ranging from 10 to 5 nm, and increased from 32 to 92 mV V−1 when the gate-length decreases from 14 to 8 nm.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.