Impact of the Ferroelectric Stack Lamination in Si Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFETs: Toward High-Density Multi-Level Cell and Synaptic Storage

Tarek Ali,Lukas M Eng,David Lehninger,Philipp Schramm,Sebastian Oehler,Joachim Metzger,Konrad Seidel,Maximilian Lederer,Ricardo Olivo,Katrin Zimmermann,Matthias Rudolph,Konstantin Mertens,Thomas Kämpfe,Johannes Müller,Kati Kühnel,F Müller ,Raik Hoffmann ,M Czernohorsky ,Róbert Binder ,J Van Houdt

doi:10.3390/electronicmat2030024

Abstract

A multi-level cell (MLC) operation as a 1–3 bit/cell of the FeFET emerging memory is reported by utilizing optimized Si doped hafnium oxide (HSO) and hafnium zirconium oxide (HZO) based on ferroelectric laminates. An alumina interlayer was used to achieve the thickness independent of the HSO and HZO-based stack with optimal ferroelectric properties. Various split thicknesses of the HSO and HZO were explored with lamination to increase the FeFET maximum memory window (MW) for a practical MLC operation. A higher MW occurred as the ferroelectric stack thickness increased with lamination. The maximum MW (3.5 V) was obtained for the HZO-based laminate; the FeFETs demonstrated a switching speed (300 ns), 10 years MLC retention, and 104 MLC endurance. The transition from instant switching to increased MLC levels was realized by ferroelectric lamination. This indicated an increased film granularity and a reduced variability through the interruption of ferroelectric columnar grains. The 2–3 bit/cell MLC levels and maximum MW were studied in terms of the size-dependent variability to indicate the impact of the ferroelectric area scaling. The impact of an alumina interlayer on the ferroelectric phase is outlined for HSO in comparison to the HZO material. For the same ferroelectric stack thickness with lamination, a lower maximum MW, and a pronounced wakeup effect was observed in HSO laminate compared to the HZO laminate. Both wakeup effect and charge trapping were studied in the context of an MLC operation. The merits of ferroelectric stack lamination are considered for an optimal FeFET-based synaptic device operation. The impact of the pulsing scheme was studied to modulate the FeFET current to mimic the synaptic weight update in long-term synaptic potentiation/depression.

Highlights

Since the introduction of the computing architecture by Von-Neumann, the architecture bandwidth limitation causes a performance bottleneck due to the latency in the data shuttling between the main memory and the processor [1]
The second aim of this paper is to explore the potential of ferroelectric lamination for an area-independent multi-level cell (MLC) FeFET operation at an improved film granularity and a reduced variability
In an MFM structure, the Pr change over the ferroelectric thickness reflects the strong role of the film stress on the stabilization of the ferroelectric phase

Summary

Introduction

Since the introduction of the computing architecture by Von-Neumann, the architecture bandwidth limitation causes a performance bottleneck due to the latency in the data shuttling between the main memory and the processor [1]. The continuous increase in the processor speed is challenged by an incomparable shortening of the memory access time; this leads to an increased frequency of the local cache miss. This is further exacerbated due to the known scaling challenges for the nearest in the hierarchy to the processor yet volatile static random access memory (SRAM) and dynamic random access memory (DRAM) concepts. The technological solutions for the Von-Neumann bottleneck cover broad concepts such as embedded nonvolatile memories [3], logic in-memory computing [4], or an alternative brain-inspired computing [5,6]

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