Abstract
In this paper we present an experimental investigation on SOI UTBB n-MOSFETs at cryogenic temperatures. The device has a silicide source/drain with dopant segregation formed by "Implantation Into Silicide" (IIS) process. The controllability of the back-gate (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">back</inf> ) on the device performance is characterized, showing that Vback is essential to tune the threshold voltage Vth and improve the subthreshold swing SS, Drain-Induced Barrier Lowering DIBL and mobility at cryogenic temperatures. The cryogenic effect on V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> , SS and DIBL with different V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">back</inf> is also studied. Furthermore, using the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">back</inf> and quantization effect at cryogenic temperature, we can optimize the SS to a lower value, providing a potential way to get ideal value of SS at cryogenic temperature.
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