Impact of source-doping gradient in terms of lateral straggle on the performance of germanium epitaxial layer double-gate TFET

Abstract

The impact of source doping gradient (SDG) in terms of lateral straggle (σ) on the performance of germanium epitaxial layer double-gate tunnel field effect transistor (ETL-DGTFET) was demonstrated by a simulation study. The non-zero tilt angle used in the ion implantation during the device fabrication process extends the implanted dopant atoms to the channel region from the source and drain which affects the performance of a device during both the ON- and OFF-states. To get a deeper insight of the impact of σ on the device performance, various DC performance parameters like Ion/Ioff ratio, average Subthreshold Slope (SSavg), and analog/RF figure of merits (FOMs) like transconductance (gm), output conductance (gds), intrinsic gain (gm/gds), parasitic capacitances and cutoff frequency (fT) were explored for σ variation from 0 to 5 nm. Circuit-level performance was also studied using an n-type ETL-DGTFET based resistive load inverter. Though the device performance is effected by the strain due to lattice mismatch between Si/Ge, it does not influence the effect of lateral straggle.