Impact of Randomly Distributed Dopants on $\Omega$ -Gate Junctionless Silicon Nanowire Transistors

Hamilton Carrillo-Nunez,Douglas J Paul,Muhamad M Mirza,Vihar P Georgiev,Donald A Maclaren,Asen Asenov

doi:10.1109/ted.2018.2817919

Hamilton Carrillo-Nunez, Douglas J Paul + Show 4 more

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https://doi.org/10.1109/ted.2018.2817919

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Abstract

This paper presents experimental and simulation analysis of an Q-shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for the 1.8-V gate overdrive with an OFF-current set at 100 nA/μm. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current-voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean I D -V Gs characteristic is in excellent agreement with the experimental measurements. Moreover, the mean I D -V Gs characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs.

Highlights

S ILICON nanowires have a wide spectrum of promising applications such as current field-effect transistors (FETs) [1], ion-selective nanosensors [2], imaging sensor [3], photovoltaics [4], energy conversion and storage [5], and qubits [6]
The electrons coming from the source need to overcome a higher potential barrier in this part of the transistor in comparison to the previous devices shown in Fig. 4(a), which is leading to a lower OFF-state current
We report an investigation of junctionless nanowire field-effect transistor (JL-NWT) from the experimental and computational point of view

Summary

Introduction

S ILICON nanowires have a wide spectrum of promising applications such as current field-effect transistors (FETs) [1], ion-selective nanosensors [2], imaging sensor [3], photovoltaics [4], energy conversion and storage [5], and qubits [6]. The low IOFF is one of the major challenges of the planar MOSFETs. Source-to-drain quantum tunnelling [7]–[9] or variability [10]–[12] is much more pronounced and deteriorate the ION/IOFF ratio in current ultrascaled devices. To overcome this problem, a variety of new architectures, including ultrathin silicon-on-insulator (SOI) [13]–[15], double gate [13], [16], FinFETs [17], [18], trigate [19], -gate [20], junctionless (JL) [21], and gate all-around nanowire FETs [22], have been developed to improve the electrostatic control of the conducting channel. The surface surrounded by the gate is increased in relation to the channel volume, improving the electrostatic control

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