Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

Mohammed Adamu Sule,Zaharah Johari,Mathangi Ramakrishnan,Michael Loong Peng Tan,Nurul Ezaila Alias,Afiq Hamzah,Norlina Paraman,Usman Ulllah Sheikh

doi:10.52549/ijeei.v8i2.1277

Abstract

Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire field-effect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (L G ) and nanowire diameter (d NW ) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (I ON ) due to the high doping concentration (N D ) of 1 x 10 19 cm -3 which leads to the improved ON-state to OFF-state current ratio (I ON /I OFF ) of about 10% than the inversion-mode device for a L G of 7 nm and the silicon d NW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high I ON /I OFF ratio. The performance was improved by introducing silicon dioxide (SiO 2 ) with high-k dielectric materials, hafnium oxide (HfO 2 ) and silicon nitrate (Si 3 N 4 ). It was found that JLNWFET with HfO 2 exhibits better electrical characteristics and performance.

Highlights

To speed up the performance of the microprocessor, the number of transistors must be double in every18 months
The N+ region is heavily doped with concentration of 1 x 1019 cm-3 in order to get high ON-state current to flow between the source and the drain
junctionless nanowire fieldeffect transistor (JLNWFET) and inversion-mode devices have been successfully designed for different gate lengths and nanowire diameters

Summary

Introduction

To speed up the performance of the microprocessor, the number of transistors must be double in every18 months. To speed up the performance of the microprocessor, the number of transistors must be double in every. To double the number of transistors means to reduce the size of transistor. As what being predicted by Moore’s law, process technology tends to be scaled down continuously [1]. The scaling process allowed more transistors to be packed in a smaller chip area and enhance the functionality of silicon on chips (SoCs). MOSFET typically used in industries due to its small size, and can be fabricated in a single integrated circuit with millions of numbers. The scaling of conventional planar transistor has reached its limit which lead to increase in short channel effects (SCEs) and sensitivity to process variation [2]. SCEs are the main limitations in the scaling of MOSFET below 10nm [3].

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