Impact of plasma-enhanced chemical vapor deposited oxide characteristics on interconnect via resistance and device performance of four-transistor static random access memory with polysilicon load resistors

Abstract

By varying the gas ratio during the process of plasma-enhanced chemical vapor deposited (PECVD) SiOx, the composition of the oxide used as the intermetal dielectric (IMD) in the device is modified, and its impact on the integrity of the interconnect metal via hole and the stability of four-transistor (4-T) static random access memory (SRAM) with poly-Si load resistors is investigated. PECVD oxides using precursors of SiH4 and N2O under various gas ratios are adopted to manipulate the Si:O atomic ratio and other dielectric characteristics. An increase in the Si atomic percent in IMD film would induce a higher via resistance. Cross-sectional scanning electron microscopy of the post- etching via holes in a Si-rich IMD sample reveals a high amount of plasma-induced polymer formation around the via holes, which is perceived as the root cause of the dimensional decrease in via hole size and a corresponding increase in via resistance. As the gas ratio of SiH4/N2O increases, the IMD films become more Si rich with a higher refractive index and an a-Si-like dangling bond (⋅Si≡Si3) density. The a-Si-like dangling bonds (⋅Si≡Si3) in IMD films serve as effective trapping centers for hydrogen or moisture above the second polysilicon load resistor and hence protect them from attack by back-end process-induced mobile charges. The resistance of these poly-Si load resistors is maintained at a high level and device performance is secured. Thus, the high quality of a 4-T SRAM device with stable load resistance, could be realized, while maintaining a low interconnect metal via resistance.