Abstract

Fundamental results for the stress dependence of the current gain and Early voltage of vertical npn and pnp bipolar junction transistors (BJTs) on (100) and (111) silicon are presented with experimental verification. These results demonstrate the direct relationship between current gain and piezoresistive coefficients and show that Early voltage is independent of stress. This information completes the data necessary for modeling the impact of stress on bipolar devices and circuits, and the modeling will facilitate simulation of the impact of process and packaging induced stress on precision analog circuits and sensors. A sample circuit simulation using the model is provided.

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