Impact of mask line edge roughness and statistical noise on next generation mask making

Abstract

As extreme ultraviolet lithography (EUVL) moves toward high volume manufacturing and pushes to increasingly smaller critical dimensions, achieving the stringent requirements for line edge roughness (LER) is increasingly challenging. For the 22 nm half-pitch node and beyond, the International Roadmap for Semiconductors requires less than 1.6 nm of line width roughness (LWR) on the wafer. The major contributor of this tight LWR is wafer resist LER and mask LER. However, in current ITRS, there is no guideline for mask LER. While significant progress has been made to reduce the resist of the LER on the wafer, it is not yet clear how much the mask LER should be improved for a 22 nm half-pitch node application. Additionally, there are various approaches to obtaining a smaller LER on the mask. It could be improved either by reducing well-known statistical noise or manipulating some process condition or material. Both approaches are effective in improving the LER, however, they shows a different result in mask CD uniformity itself. In this paper, in addition to setting the criteria of the mask LER, we will discuss how tight the mask LER is required to be and what kind of approach is desirable with regards to the LER and CD uniformity. Finally, an analysis of the LER and CD variation provides some insights into the impact of the next generation mask infrastructure.