Abstract
Feedback timing recovery schemes suffer from the delay in the feedback loop. Because this delay can be large in optical systems, especially when digital signal processing is implemented in FPGA, the performance of the phase-locked loop can be compromised when it has large loop bandwidth. In this letter, the performance of the digital feedback timing recovery scheme based on Gardner's detector is analyzed considering the delay in the loop and the phase noise that affects the local oscillators used for clocking data converters. Numerical results reported in this letter show that simulations closely fit the analysis.
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