Impact of Interface Traps and Surface Roughness on the Device Performance of Stacked-Nanowire FETs

Abstract

In stacked-nanowire field-effect transistors (stacked-NW FETs), the effect of nanowire surface roughness (NWSR) and random interface traps (RIT) on device performance variation is investigated. The 3-D NWSR profile is applied to the surface of the nanowires, and then, the interface traps are generated and randomly placed in the interfacial layer between the silicon and high-k. First, the interaction between NWSR and RIT in a single-NW FET is investigated; the NWSR-induced performance varia- tion is not independent on the RIT-induced variation. Then, the correlation of NWSR profiles and RIT in stacked-NW FETs is explored. The degree of correlation between the NWSR profiles of stacked-NWs is varied in three cases: 1) positively correlated; 2) negatively correlated; and 3) uncorrelated. Without RITs, the NWSR-induced performance variation of the stacked-NW FETs dramatically increases as the NWSR profiles of the nanowires become positively correlated. However, with RITs, the more positively correlated the NWSR profiles of the nanowires, the larger is the ${V}_{T}$ variation that the interface traps induce. Interface traps barely affect the ${V}_{T}$ variation of the negatively correlated NWSR profiles. The variation of current slightly decreases because interface charge scattering degrades the mobility of the carriers.