Impact of Gate–Source/Drain Underlap on the Performance of Monolayer SiC Schottky-Barrier Field-Effect Transistor

Abstract

Schottky-barrier field-effect transistors (SBFETs) based on 2-D semiconductorshad been investigatedas a substitute for a conventional metal-oxide-semiconductor field-effect transistor (MOSFET) based on bulk silicon in the field of high-performance (HP) device. Especially, the monolayer SiC has been studied because it has a large band gap, which results in reducing the short-channel effect. In this article, the gate-source/drain underlap-dependent characteristics of HP SBFETs based on monolayer SiC with 5.1and 4.6-nm gate lengths are investigated through ab initio simulations. The performances of the 5.1-nm monolayer SiC SBFET are degraded by the gate-source/drain underlap. The gate-source/drain underlap, however, shows the different improved performances for the 4.6-nm monolayer SiC SBFET. The gate-source underlap could enhance the ON-current to 2792 μA/μm and the gate-drain underlap can enhance the ON-current to 1754 μA/μm, which all far exceed the International Technology Roadmap for Semiconductors (ITRS) requirement.