Abstract
The impact of gate line-edge roughness (LER) on the performance of the planar germanium-source tunnel FET with gate length Lg = 30 nm is studied via 3-D device simulation. Depending on the source formation process, gate LER can result in source LER. Therefore, two extreme cases of the source edge profile are considered herein: smooth edge and rough edge. Threshold voltage VT variation due to gate LER is found to be minimal in each case, as compared to VT variation caused by random dopant fluctuations (RDF). Gate LER is also found to have negligible impact on the off-state leakage current floor. In the case of a source with smooth edge, gate-LER induced variation in on-state drive current can be significant.
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