Impact of Dwell Time and Lower Potential Limit during Voltage Cycling on PEM Fuel Cells Catalyst Durability

Abstract

Hydrogen proton exchange membrane fuel cells (PEMFC) are the most promising fuel cell technology for automotive applications. However, for full commercialization of the technology, the fuel cell stacks still need to overcome the durability issues caused by the degradation of the cathode electrode during load cycling. In fact, load cycling, which corresponds to high and low cathode potentials, causes oxidation of platinum (Pt) at upper potential limit (UPL) and reduction of this oxide layer to fresh Pt surface at lower potential limit (LPL), leading to dissolution and subsequent migration or redeposition of Pt ions that results in degradation of electrochemical surface area (ECSA) of Pt and loss of performance [1]. In order to simulate load cycling between relevant operation potentials and age the cells faster in the laboratories, appropriate voltage cycling (VC) based accelerated stress tests (ASTs) have been developed which mimic the Pt ECSA loss in the cathode electrode due to load variations. Various voltage cycle profiles in VC-ASTs, such as, LPL, UPL, and dwell time at each of these vertices could substantially impact the rate of cathode degradation [2]. In this work, the impact of LPL and UPL dwell time under different values of LPL on catalyst degradation is systematically investigated.In this regard, Kneel et al. [3] investigated the effect of exposure time to high potentials on degradation rate considering both symmetric and asymmetric (square wave cycles with a different dwell time at upper and lower voltage limits) square waves cycling between 0.6 and 0.9 V. They kept the cycle duration (sum of LPL and UPL dwell time) constant at 60 s while changing the LPL and UPL dwell time accordingly: 2 s-58 s, 30 s-30 s, and 58 s-2 s. As they observed greater degradation rate per cycle for longer dwell times at UPL, they concluded that the primary factor causing catalyst degradation is the dwell time at high potentials, rather than the cycle duration. Additionally, Young et al. [4] evaluated the impact of UPL dwell time when the LPL dwell time, instead of cycle duration, was kept constant at 30 s throughout the experiments. They varied the dwell time at high potentials (5, 20, 60, 300, and 600 s) during square wave voltage cycling between 0.6 and 1.4 V and found an increasing degradation per cycle with increasing dwell time at high potentials. However, at this high UPL (1.4 V), ECSA loss is not only caused by Pt dissolution but also by carbon corrosion. Indeed, when considering automotive applications, the upper potential is limited to the open circuit voltage (OCV), which is lower than 1.0 V during normal operation. Therefore, to ensure that the experiments are appropriate for these applications, in this work the degradation of the catalyst is studied under square wave voltage cycling between 0.6 to 0.95 V in a hydrogen/air atmosphere while keeping one of the dwell times fixed from one experiment to another. The LPL and UPL dwell times of the first three experiments are 3 s-3 s, 3 s-10 s, and 10 s-3 s, respectively. The ECSA loss is measured by cyclic voltammetry for each AST. The same set of experiments is then repeated for LPL of 0.8 V to examine the impact of complex interplay of the LPL and the dwell times on the ECSA degradation as the reduction rate of oxide layer in a VC-AST with a UPL near OCV (0.95 V) is expected to vary with different LPLs. These experiments could complete the previous findings in the literature by systematically changing potential limits and dwell times and therefore help better understand the underlying mechanism of Pt loss during load cycle operation. Acknowledgements This research was supported by the Natural Sciences and Engineering Research Council of Canada, Canada Research Chairs, and Simon Fraser University Community Trust Endowment Fund.