Impact of Dielectric Pocket on the Performance of Double Gate TFET

Abstract

To improve the ambipolar behavior, Dielectric Pocket (DP) is incorporated in the Double Gate Tunnel Field Effect Transistor (DGTFET). The DP plays a key role in the ambipolar conduction of TFET. The proposed device Dielectric Pocket DGTFET (DP-DGTFET) has been demonstrated using a 2D TCAD simulator. The DP length and thickness are optimized to increase the minimum tunneling width near the channel-drain junction, which indeed reduces the ambipolar conduction of the device without affecting the ON-state current, subthreshold swing, and the output characteristics. Moreover, using a high-k material instead of low-k as a dielectric pocket, enhance the device performance in terms of ambipolar behavior. Additionally, the analog performance of the proposed device was also investigated. It is observed that the presence of DP enhances the device performance by reducing the gate to drain capacitance (C gd ); whereas, the presence of gate to drain overlap has a negative impact (increases C gd ) on the proposed device. It is demonstrated that the gate on drain overlap along with the DP in DGTFET enhances the DC performance of the device by reducing the ambipolar current.