Abstract
Long term stability of gate oxides is a crucial aspect for the reliability of SiC MOSFETs. In this paper the impact of gate bias driven degradation mechanisms on electrical parameters have been investigated for SiC MOSFETs with planar and trench MOS structure. Therefore, high temperature gate bias tests have been carried out. The periodically increased gate voltage until the time dependent dielectric breakdown led to an increase of the threshold voltage and to a change of the internal capacitances. To capture the behavior of the threshold voltage precisely, the hysteresis method has been applied during intermediate read-outs. Additionally, the switching behavior of the specimens has been measured in double pulse tests to analyze the impact of the shifted electrical parameters on switching losses and waveforms.
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