Gate Oxide Reliability of 1.2 kV and 6.5 kV SiC MOSFETs under Stair-Shaped Increase of Positive and Negative Gate Bias

Abstract

In this paper the gate oxide reliability of SiC MOSFETs has been tested under different stress conditions. Discrete devices of the 1.2 kV class with planar and trench MOS-structure have been examined under positive and negative stair-shaped increased gate bias until the time dependent dielectric breakdown (TDDB). This test procedure was developed to expose extrinsic failures in high temperature gate bias tests. Additionally, three prototype power modules equipped with 6.5 kV SiC MOSFETs have been tested under positive, negative constant voltage gate bias and positive stair-shaped increased gate bias. The threshold voltage together with the output characteristic has been recorded before test start and after every stress period. A significant impact from the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS(Th)</sub> -drift on the output characteristic is shown. Hence, it is recommended to consider the TDDB and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS(Th)</sub> -drift for lifetime predictions.