Impact of Channel, Stress-Relaxed Buffer, and S/D Si1−xGe x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering

Abstract

Stress-engineered fin-shaped field effect transistors (FinFET) using germanium (Ge) is a promising performance booster to replace silicon (Si) due to its high holes mobility. This paper presents a three-dimensional simulation by the Sentaurus technology computer-aided design to study the effects of stressors—channel stress, stress-relaxed buffer (SRB), and source/drain (S/D) epitaxial stress—on different bases of FinFET, specifically silicon germanium (SiGe) and Ge-based, whereby the latter is achieved by manipulating the Ge mole fraction inside the three layers; their effects on the devices’ figures-of-merits were recorded. The simulation generates an advanced calibration process, by which the drift diffusion simulation was adopted for ballistic transport effects. The results show that current enhancement in p-type FinFET (p-FinFET) with 110% is almost twice that in n-type FinFET (n-FinFET) with 57%, with increasing strain inside the channel suggesting that the use of strain is more effective for holes. In SiGe-based n-FinFET, the use of a high-strained SRB layer can improve the drive current up to 112%, while the high-strain S/D epitaxial for Ge-based p-FinFET can enhance the on-state current to 262%. Further investigations show that the channel and S/D doping are affecting the performances of SiGe-based FinFET with similar importance. It is observed that doping concentrations play an important role in threshold voltage adjustment as well as in drive current and subthreshold leakage improvements.