Impact of body bias on delay fault testing of nanoscale CMOS circuits

Abstract

A body biasing technique has recently been proposed for microprocessors in sub-100 nm technology generations. It is shown that forward body bias (FBB) reduces the leakage power and suppresses the effect of process variation while reducing the complexity of dual V/sub th/ technology. We study the effect of body bias on the delay fault testing of CMOS circuits. We analyze the impact of both fixed and adaptive body biasing techniques on test cost and the quality of test. Statistical analysis on several benchmark circuits shows that the adaptive body biasing design have the most effective impact on delay fault by maintaining the test cost at its minimum under process variation while ensuring the test quality at its highest level.