Impact of Aging on Soft Error Susceptibility in CMOS Circuits

Abstract

Aging and soft errors are the two most critical reliability issues for nanoscale CMOS circuits. The soft error becomes more severe if the circuit performance degraded with the aging. In this paper, we address the issue of analyzing the effects of Negative Bias Temperature Instability (NBTI) mechanisms on Integrated Circuit’s (ICs’) soft error susceptibility. We first analyzed the critical charge sensitivity of two-input NAND gate for various operating temperatures with three years of stress. Results show that the critical charge decreases with the temperature and has the maximum degradation of 19.98% if the input AB is at 01 logic compare to 12.06%, 16.8%, and 11.15% for 00, 10, and 11. Further, we validated the results with c17 from ISCAS’85 benchmark suite to estimate the soft error. The critical charge at the sensitive node of the c17 circuit is decreased by 9.87% for the worst case input pattern 00010. Thus thorough investigation of the critical charge provides a measure for the soft error susceptibility with the NBTI effect on ICs.