Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-k/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors

Abstract

We have clarified the effects of activation annealing temperature on the negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime improvement of HfSiON/TiN gate stack p-type metal–oxide–semiconductor field effect transistors. Higher-temperature annealing is effective for the improvement in NBTI and TDDB lifetime. This is due to the Si substrate oxidation occuring during the high-temperature annealing, resulting in interface defect state reduction. Annealing is also effective for reducing threshold voltage with consequential improvement in device performance.