Impact ionization MOS (I-MOS)-Part II: experimental results

Abstract

Part I of this paper dealt with the fundamental understanding of device physics and circuit design in a novel transistor, based on the field-effect control of impact-ionization (I-MOS). This paper focuses on experimental results obtained on various silicon-based prototypes of the I-MOS. The fabricated p-channel I-MOS devices showed extremely abrupt transitions from the OFF state to the ON state with a subthreshold slope of less than 10 mV/dec at 300 K. These first experimental prototypes of the I-MOS also showed significant hot carrier effects resulting in threshold voltage shifts and degradation of subthreshold slope with repeated measurements. Hot carrier damage was seen to be much worse in nMOS devices than in pMOS devices. Monte Carlo simulations revealed that the hot carrier damage was caused by holes (electrons) underneath the gate in pMOS (nMOS) devices and, thus, consequently explained the difference in hot carrier effects in p-channel versus n-channel I-MOS transistors. Recessed channel devices were also explored to understand the effects of surfaces on the enhancement in the breakdown voltage in I-MOS devices. In order to reduce the breakdown voltage needed for device operation, simple p-i-n devices were fabricated in germanium. These devices showed much lower values of breakdown voltage and excellent matches to MEDICI simulations.