Immunity to random fluctuations induced by interface trap variability in Si gate-all-around n-nanowire field-effect transistor devices

Abstract

The impact of variations in the donor and acceptor interface trap distributions on the fluctuation characteristics of 7-nm-node Si gate-all around n-nanowire FET (n-NWFETs) is analyzed in a hardware-calibrated quantum-corrected three-dimensional (3D) drift–diffusion (DD) numerical simulation framework. Shifting the energy position of the peak in the acceptor trap density distribution (Dit) induces greater surface potential fluctuations and carrier mobility degradation compared with variation of the donor traps. It is found that single-charge traps (SCTs) and random interface traps (RITs) induce larger V $$_{\text {T}}$$ and drain-induced barrier lowering (DIBL) variations, along with charge neutrality level (CNL) variations induced by interface trap fluctuations. The Si n-NWFET shows better immunity to interface trap variability when the CNL is located between the midgap and the conduction-band edge. For future sub-7-nm high-performance NWFET logic devices, such interface trap variability will be one of the major sources of random fluctuations at the device level.