Image Smoothing Based On FPGA

Maha A.R Hasso,Farah Saad Al-Mukhtar

doi:10.33899/edusj.2013.89910

Abstract

Programmable logic is emerging as an attractive solution for many digital image processing applications. As image sizes and bit depths grow larger, software has become less useful in the image processing, Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of algorithms suited to image processing applications, the unique architecture of the FPGA has allowed the technology to be used in many such applications encompassing all aspects of image processing. Image smoothing is one of image processing applications, it often done to reduce the effect of pixel noise in images. This paper presents VHDL architectures (that allow description of the structure design of FPGA) to implement two of image smoothing filters: a) averaging filters b) median filters This research is also applying the filters on FPGA. The results proves high-speed performance of the algorithms that rely on hardware and software compared to software alone, as it appeared very big difference in the speed of execution, depending on the hardware devices that showed the speed of the implementation of the scale of nanosecond, while the software application of algorithms is measured in seconds. The software was implemented in this research using MATLAB 2010 language code as well as the VHDL language to deal with use of FPGA device, which was of a kind (Xilinx XC3S500E Spartan-3E).

Highlights

Image processing is considered to be one of the most rapidly evolving areas of information technology, with growing applications in all fields of knowledge
In this work pointer is using to reach the positions in RAM instead of using the first in first out implementation (FIFO) which is reduce the complexity of the algorithms implementation, it reduce the size of the algorithms
Hardware dividers on Field Programmable Gate Arrays (FPGAs) are quite large and slow, we use the bit shifting method of division. Since this is only possible with powers of two, a divide by 8 was implemented instead of a divide by 9, as was planned in the algorithm’s design; Figure 2 shows a sketch representation of the mathematics of the hardware averaging filter; wile figure 3 shows the schematic design for the average filtering; figure 4 shows the simulation time result of average filtering in VHDL, and figure 5 shows the image after applying the average filtering in MATLAB and in VHDL

Summary

Introduction

Image processing is considered to be one of the most rapidly evolving areas of information technology, with growing applications in all fields of knowledge. The performance requirements of image processing applications have continuously increased the demands on computing power, especially when there are real time constraints. In order to accelerate image processing, there are different alternatives ranging from parallel computers to specialized Application Specific Integrated Circuits (ASIC) architectures. In the spatial domain, filtering is a pixel neighborhood operation. Neighborhood of pixels is called windowing operators that are use a window to calculate their output. The work in this paper is based on the usage of gray scale image smoothing using these pixel windows to calculate their output. A pixel window may be of any size and shape, a square 3x3 size was chosen for this application because it is large enough to work properly and small enough to implement efficiently on hardware

Related work

The Implementation of the Filters in the Proposed Work

Conclusion and Result Discussion