Image Multiplication Using Novel 4:1 Approximate Compressor*

Abstract

Energy-efficient designs are the need of the hour for signal and image processing applications that are error-tolerant. The paper proposes a new 4:1 approximate arithmetic-based compressor developed by analyzing the probability-based tactics that have a higher degree of precision when implemented. Approximate n × n multiplier is designed using the proposed varying probability-based compressors. To validate the effectiveness of the new compressor, a 16 × 16 multiplier is designed. The n × n bit multiplier will have 2 n columns of partial products(PP), in which the least significant n−1 columns are designed using the novel approximate 4:1 compressor and most n + 1 columns are designed with the exact compressor. The results of the 16-bit multiplier are superior to the performance of the exact multiplier in terms of power, area, power-delay-product (PDP), and area-delay-product (ADP) typically by 39 % , 20 % , 44 % , and 26 % respectively for Design 1 and 14 % , 24 % , 30 % , and 21 % , respectively for Design 2. The Peak Signal to Noise Ratio(PSNR), Mean Square Error(MSE), and Structural Similarity Index Measure(SSIM) for the output images processed by new approximate multipliers are acceptable when compared with precision and energy.