IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system

Abstract

In order to increase the circuit yield, 2.5D technology have been introduced to partition a single large circuit in multiple circuits, which are tested before bonding and then assembled in 3D onto a passive silicon interposer. Active interposer is nowadays envisioned in order to provide added values within the interposer and the 3D complete system. The testability of 2.5D interposers have already been well studied but no 3D DFT have already been proposed for active interposers. In this paper, a 3D Design-for-Test architecture is proposed for testing multi-chips stacked onto an active interposer. The 3D-DFT is based on a chiplet footprint architecture, allowing the modular test of any chiplets, and is implemented using IJTAG IEEE1687 standard, offering easy test pattern retargeting from chiplet pre-bond test to the 3D circuit final test. The proposed 3D-DFT architecture and the associated 3D test flow have been fully applied onto a 3D active interposer circuit prototype and used extensively to test interposer active links, interposer passive links and all embedded memory BIST engines.