Identifying process window marginalities of reticle designs for 0.15/0.13-μm technologies

Abstract

ABSTRACT The complexity of Resolution Enhancements Techniques (RET) will increase dramatically in the next four generations of optical lithography, requiring careful qualification of new reticle designs when they arrive at the wafer fab and before commiting them to printing product. Low k1 and high MEF lithography increase theprintability and frequency of yield impacting repeating defects from reticle defects and RET layout errors.Therefore, reticle qualification must include qualifying the reticles for mask processing errors as well as for RET design rule violations. The former is performed on a reticle inspection tool and the latter on a wafer inspection tool after printing wafers with a specific layout using the reticles of interest. The output from the wafer inspection tool followed by detailed analysis provides information on the regions of marginality within the reticle field or features within the die which have smaller process window than expected. We call this the P rocess W indow Q ualificationOutput, PWQ Output and it can be applied to single and multi-die reticle designs.Once these locations are identified by PWQ and the features are determined to be critical to thefunctionality of the device, further process window analysis on the CD SEM is performed to identify if sufficient process window overlap exists between these features and all other critical features in the device. If the process window overlap of the marginal features with other critical features is acceptable, the reticle can be used to print product. These marginal regions are then carefully monitored on product by CD Metrology. If insufficient overlap in the process windows is found, the PWQ Output features are overlayed with the CAD design and a design fix might be required, followed by the manufacturing of a new reticle. In this paper we describe how we used the PWQ methodology to identify RET design errors for three different reticle designs; in the first example, the marginal feature is an OPC sizing error causing the below design rule spacing in a 0.13 m Gate reticle design to bridge within the process window and the second example is that of a marginal feature associated with improper biasing and a phase error for an Attenuated PSM reticle. The final example shows how PWQ was used to verify the printing of an assist feature within the process window for a Gate 0.13 m reticle.Keywords: PWQ (process window qualification), reticle, RET, lithography