Rapid yield ramp using closed loop DFM and overlay process window qualification flow

Abstract

At advanced nodes (sub 28nm), it has become a major challenge to design and verify integrated circuits to achieve high yield. The complex interactions of design and manufacturing process need to be bridged by Design for Manufacturability (DFM) / Design for Yield (DFY). With further shrinking of process technology, the on-chip variation worsens for each technology node. As a result, traditional defect detection methodologies also become more challenging. Interlayer and/or overlay driven defects have begun to plague lithography patterning. Traditional Process Window Qualification (PWQ) (focus and dose modulation) alone may not define the true process window. Overlay has become an additional factor to aid in determining the complete process window. DFM brings manufacturing variability awareness into the design to address the yield limiting configurations using pattern matching and recommended rules. In this paper, we propose a closed loop DFM and Overlay Process Window (OPW) qualification flow to identify yield-limiting configurations and address them early in the product yield ramp for faster time-to-market (TTM).