Identifying Contributions to Electrical Instability in High-k Gate Stacks: As-Grown vs. Generated Defects

Abstract

Stress-induced changes in the high-k gate stack electrical characteristics may originate in both the Hf-based dielectric film and the SiO2-like interfacial layer, in which instability could be induced by different mechanisms. In this work, we focus on the contributions from as-grown defects and defect precursors in each of these layers, as well as stress-generated defects, under low and high voltage stress regimes. Physical data, consistent with ab initio calculations, is presented in support of proposed theoretical explanations for the mechanisms that give rise to electrical performance.