Identification of plasma induced failure modes in the development of a bipolar‐complementary metal–oxide–semiconductor process

Abstract

Development of a bipolar‐complementary metal–oxide–semiconductor process encountered metal–oxide–semiconductor (MOS) device failure behaviors that were traced to a single processing plasma source. Despite the fact that the process employed relatively thick 500 Å MOS gate oxides and was made in a manufacturing line that also produces a complementary metal–oxide–semiconductor product with gates below 200 Å, significant plasma damage effects were identified. Four distinct failure signatures were observed: shorted n‐channel metal–oxide–semiconductor transistor (NMOS) gates, leaky NMOS gates with functioning channels, parasitic depletion mode conduction at the ends of the enhancement NMOS device channel, and p‐channel metal–oxide–semiconductor transistor (PMOS) threshold shift as observed in a differential amplifier input offset. Test devices were specifically designed to monitor plasma damage through various gate antenna configurations. Device protection fuses were also employed to identify the cause of the failures as electrical damage induced during the backend of wafer processing. Although the methodology was successful, the experience points toward significant improvements that can be made and will be employed in future development and characterization efforts on a routine basis. Sequential characterization of device performance from the first metal out quickly identified the plasma enhanced chemical vapor deposition tool used for final passivation deposition as the primary contributor to the plasma damage. Subsequent process flow changes did eliminate this source of plasma damage.