IC yield estimation at early stages of the design cycle

Abstract

A yield prediction in the early stage of the design cycle can give positive impacts on cost and quality of IC manufacturing. However, the lack of prediction tool, that do not rely on layout data, makes it difficult to estimate the chip yield in the early design phase. This article describes yield prediction models for random logic and SRAM blocks using inductive fault analysis. The proposed model predicts defect sensitive area early in the design cycle as a function of simple circuit parameters without using any layout data. We applied both models to commercial ASIC products for validation. The IC yield estimation using the sensitive area model showed an acceptable accuracy of a well below 10 % error.