Hybrid parallel counters - domino and threshold logic

Abstract

Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 /spl times/ 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.