Custom formal verification technique for partial product reduction tree

Abstract

Wide partial product reduction tree (PPRT) circuits are ideal for high speed low area inner products, and can be designed using merged arithmetic and a speed-optimized reduction algorithm. While the performance of small architectures can be checked successfully using a simulation, the problem with using a simulation to check a merged architecture model is that a merged structure results in a wide PPRT, which produces an extremely high number of partial products. Because the time required to test all of the partial product values is prohibitive, only a small percentage of the possible values can be tested, providing no real picture of the circuit's functionality. In this paper we present a method (implemented in the C programming language) of deriving the functionality of a PPRT circuit from its topology, and we present a custom PPRT fast simulation setup that can detect the most of the crisscross net errors.