Hybrid parallel circuit simulation approaches

Abstract

In this paper, we address the parallel timing simulation of synchronous VLSI designs on networks of workstations (NOWs). Our approaches exploit the performance gap between cycles based simulators and timing simulator techniques and combine both methods to speedup timing simulation. Based on the technique we developed four different simulation methods, which are characterized by removing some communication between the timing simulators. In particular, we execute a timing simulator on each node of the NOW and use cycle-based simulation to produce synchronization information required by the timing simulators. One of our methods even does not need any communication at all and is hence well suited for parallel simulation on NOWs, which are typically characterized, by low bandwidth and high communication latency. Simulation results show that a significant speedup can be achieved even for very small circuits.