Efficient parallel timing simulation of synchronous models on networks of workstations

Abstract

In this paper we address the parallel timing simulation of synchronous VLSI designs on a network of workstations (NOWs). We suggest combining cycle based and conventional timing simulation techniques to achieve fast timing simulation even on NOWs which are typically characterized by low bandwidth and high communication latency. In particular we execute a timing simulator on each node of the NOW and use cycle based simulation to produce synchronization information required by the timing simulators. As synchronization information is generated exclusively by the cycle based simulator there is no need for any communication between the timing simulators. To verify the feasibility and performance of our approach we simulated several circuits using our approach. The results show that a significant speedup can be achieved even for very small circuits.