Hybrid Monolithic 3-D IC Floorplanner

Abstract

With continued technology scaling, interconnects have become the bottleneck in further performance and power consumption improvements in modern microprocessors. 3-D integrated circuits (3-D ICs) provide a promising approach for alleviating this bottleneck and enabling higher performance while reducing the footprint area, wirelength, and overall power consumption. Among various 3-D IC solutions, monolithic 3-D ICs stand out as they can utilize the third dimension most efficiently owing to high-density monolithic intertier vias. Monolithic integration is possible at different levels of granularity: block level, gate level, and transistor level. A hybrid monolithic design has modules implemented in different monolithic styles to further optimize the design objectives such as area, wirelength, and power consumption. However, a lack of electronic design automation tools makes the hybrid monolithic 3-D IC design quite challenging. In this paper, we introduce the first hybrid monolithic 3-D IC floorplanner. We characterize the OpenSPARC T2 processor core using different monolithic implementations and compare their footprint area, wirelength, power consumption, and temperature. We show, via simulations, that under the same timing constraint, a hybrid monolithic design offers 48.1% reduction in the footprint area and 14.6% reduction in power consumption compared to those of the 2-D design at the cost of higher power density and slightly higher temperature.