Abstract
The FDSOI (Fully Depleted Silicon on Insulator) technology has proven to be a promising candidate for next CMOS generations, due to its very high speed, low power and moderate cost. In addition, recent reports on combining FDSOI with high k metal gate have raised considerable interest since it is able to achieve low power devices. But it should be noticed that a drawback of using this SOI structure is that the thickness of active Si and buried oxide (BOX) limit the implementation of ESD protections. Hybrid co-integration of SOI thin film with bulk will be a solution of this problem, and also makes it possible to better control Vt with use of back biasing. This paper will demonstrate experimentally about one approach of the hybrid co-integration scheme in FDSOI CMOS process. The influence of back biasing on threshold voltage and ESD protection will also be discussed.
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